Reference is now made to FIG. 1 that shows a conventional system 10 for providing column access to a RAM, and FIG. 2 that illustrates typical waveforms for a write operation. The column access system 10 comprises a column counter 12 that receives an external n-bit address signal ExtAdd&lt;0:n&gt; to produce a column address CA&lt;0:n&gt;. An external command ExtCmd defining a RAM operation is supplied to a command decoder 14 that decodes the command and produces signals required to execute it. For example, if the ExtCmd defines a write operation, the command decoder 14 produces a write enable signal WE, a global input/output equalize control signal GIOEQ, and a column decode enable signal CDE.
An address decoder 16 receives the column address CA&lt;0:n&gt;, together with the column decode enable signal CDE, to produce a decoded column address AYD supplied to a column select line (CSL) generator 18. The write enable signal WE and the equalize control signal GIOEQ, together with data ZWDD, are supplied to a write driver 20 for producing a global input/output signal GIO and a complementary global input/output signal ZGIO to drive a global input/output pair GIO/ZGIO coupled to a DRAM array 22. The global input/output pair GIO/ZGIO is used for providing data transfer during writing and reading operations. A column select line signal CSL&lt;0:n&gt; produced by the CSL generator 18 selects a column in the DRAM array 22 for writing the data
As shown in FIG. 2, a new column address CA is generated and latched in the column counter 12 at the rising edge of a clock signal CLK during a write cycle. Such latching allows the column address to be isolated from the external address ExtAdd. Thus, the external address ExtAdd can be changed without changing the generated column address CA. The write enable signal WE is activated after the column address CA is initiated.
As a result, a new CSL signal based on the new column address CA cannot be produced until the current write or read operation is completed. For example, when a precharge command is issued during a write operation, a precharge operation is delayed by the write recovery time tWR equal to the time period between the raising edge of the clock corresponding to the write operation and the raising edge of the CSL signal.
The write recovery time tWR may be greater than 1 clock cycle. In this case, a no operation command NOP must be issued between the write operation and the precharge operation.
Accordingly, it would be desirable to provide a column access system that allows the write recovery time to be reduced to eliminate a no operation cycle between a write operation and the next operation, such as a precharge operation.
Further, in the conventional column access system, the GIO/ZGIO pair is driven only when the write enable signal WE and other write control signals, such as the column decode enable signal CDE, are at a high level. Therefore, the signals WE and CDE has to be latched in the command decoder 14 to maintain them at a high level as long as a write operation occurs. Thus, in high-frequency applications, when the clock cycles are short, the write enable signal WE and the column decode enable signal CDE cannot be reset until the next clock cycle begins. As a result, the next operation is delayed.
It would be desirable to provide a column access system that allows the write control signals to be reset in the.current clock cycle to reduce a delay between operations.